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Micrel
Auto-Polling
The auto-poll block (Figure 3) contains a low power
oscillator that drives the sleep timer when the rest of
the device is powered down. It also contains circ uits to
MICRF219
that a window time set longer th an this will result in all
bits being tested as bad and th e device will remain in
sleep polling mode. Now, whe n the serial command
check whether the received bits are go od.
Auto-
sets bit D15 high, the device will go to sleep for the
polling is controlled by bit D15 in the serial regis ter, in
conjunction with bits D12, D13, D 14 to set the sleep
timer period. Bits D7, D8, a re used for control of the
bit-check operation and bits D9, D10, D11 a re u sed to
adjust the sensitivity of the bit-check action.
Auto-Polling without Bit-Checking
For simple auto-polling without bit-checkin g, s end a
serial command with bit D15 set high and bits D12,
D13, D14 set to the desired sleep time. T he device
will go to slee p for the programmed timer du ration
timer period and will then awak e to receive and check
bits. The device will output dat a again at DO as soon
as the programmed numbers o f good RTZ bits have
been received. If a bad bit is seen, the device will
return to sleep mode and poll a gain for good bits after
the sleep period. Both high and low periods are
checked for each RTZ bit. The device will continue to
check bits until sufficient good bits e nable the device
to wake up, or bad bits return th e device to sleep.
Operation
then wake up to receive data if it is present.
The
Received pulse edges trigg er a programmable
device will stay awake until serial bit D15 is se t low,
then set high again, to enable a further sle ep peri od.
The sleep duty cycle may be controlled by the timing
of serial commands.
Auto-Polling with Bit-Checking
For auto-polling with bit-checking, the seri al re gister
bits D7and D8 need to be set for the numbe r of bits to
be checked as good, before the receiver outputs data
at the DO pin. The bit-check window bits D9, D10,
D11 must also be set to match the data period. The
shortest default window time gives the least critical bit
check action. For better discrimination, the window
setting may be increased up towards the normal
minimum time expected between data edges. Note
window timer clocked by the refe rence frequency. If
the next pulse edge falls within this window the bit is
flagged as bad. Detected good bits are counte d and
the device will wake up once sufficient pulses have
been received. Two bad pulses or a lack of pulses will
cause the device to go to sle ep for a further sleep
timeout peri od.
Squelch
During normal operation, if four or less out of eight bit
pulses are good, the DO output is squelched. If good
bit count increases to seven or more in any eight
sequential bits, squelch is disabled allowing data to
output at DO pin.
June 2011
10
M9999-060811
(408) 944-0800
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